IEEE Std C37.91-2021
Protecting Power Transformers
6.4.2 External Faults
6. Relay Currents
6.4 Performance of CTs
6.4.2 External Faults
1. Scenario in Figure 1(a):
Configuration: A transformer is connected to single bus arrangements on both the source and load sides.
Fault Location: An external fault is located at F1.
Behavior: The fault currents flow through the transformer. This is referred to as "through-currents".
Current Limitation: These fault currents are limited by a series combination of the source impedance (Zs) and the transformer impedance.
CT Saturation: The CTs (Current Transformers) are not likely to saturate if they are selected considering the levels of the fault currents and the relay burden (including the burden due to the leads connecting the CTs to the relay).
2. Scenario in Figure 1(b):
Configuration: A transformer is connected to a breaker-and-a-half bus arrangement on the source side and a single bus arrangement on the load side.
Fault Location: An external fault is located at F1, same as in scenario 1(a).
Behavior: Similar to scenario 1(a), the fault currents flow through the transformer.
Current Limitation: Same as in scenario 1(a), the fault currents are limited by the source and transformer impedances.
CT Saturation: Similar considerations for CT selection as in scenario 1(a) apply here as well.
3. Scenario in Figure 1(c):
Configuration: Same as in scenario 1(b), but the fault location is different.
Fault Location: An external fault is located at F2.
Behavior: The fault current does not flow through the transformer but flows through the two CTs provided on the breaker-and-a-half bus that form part of the transformer protection scheme.
Current Limitation: The levels of primary currents in CTs would be substantially large because they are limited only by the source impedance.
CT Saturation: One or both CTs may saturate due to the high fault current. The unequal outputs of the CTs cause differential currents to flow in the operating coils of the differential relay.
Solutions for Transformer External Fault:
Time overcurrent relays with high settings can be used to avoid false trips. Original paragraph "Time overcurrent relays, without restraint, can overcome this problem only by having their pickup and time dial settings made sufficiently high to override this false differential current." It seems like it asks to replace differential relay with 51 which I think it should not be recommended.
Percentage differential relays are more advantageous due to faster operation and security with reasonable sensitivity.
Restraint elements should be applied in each CT circuit.
The burden of each CT secondary circuit should be checked to ensure that it doesn't exceed the permissible ratio errors recommended by the relay manufacturer.